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Wednesday, 21 December 2016

Caches, Latency, RISC & CISC: How Does a 386 Beat a 1.6GHz Celeron?

I'm rewriting this article, because I've decided it was a bit shit.

Ultimately, it costs more to complete certain instructions on a CPU that's designed to work with cache, especially when there are 3 levels of it, than it does to complete on a simpler architecture like the 80386. I'll explain it better at some point soon.

Hopefully.